Tokyo, Japan Nov. Capabilities range from constraint correctness and completeness checking through structural analysis and advanced formal techniques for the verification of timing exceptions. By ensuring that timing constraints remain consistent with the design intent as the design undergoes transformations from RTL through final netlist, implementation iterations are reduced substantially. SpyGlass-Constraints structural and formal verification capabilities are already incorporated into version 3. STARC engineers conducted an exhaustive evaluation of the new SDC equivalence checking capability on a broad range of test case designs, and were able to show that this technology added even further significant value. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation.
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There are three steps to be performed: 1. Goal Set up and Run: Specify the goals, the severity level of tool run initial rtl, detailed rtl and rtl handoff levels and run the goals. Analyze the results: The results of the tool run on the set up goals are analyzed and reports are generated.
Design Setup: a. Adding files: Click Add File s to add design files. They can be automatically generated in latter stages. For now, you can add just design files ie. You can omit ram files as they are out of the design. Run Design Read. This will run very basic rules to check if all the design modules are present, hierarchy etc. After the Run Design Read button is executed, the tool will ask for the project name. After Run Design Read is executed, messages can be seen in the below session log.
There are three type of messages that will be generated in session log name Info, Warning and Error messages. We can three severity levels in Goal setup and run namely initial rtl, detailed rtl and rtl hand- off, with rtl handoff severity level being run with more stringent rules. Select Central Set up for Designing clocks, resets and autocaseanalysis constraint files. Here Blackboxes can be found out if present.
If they are present they can be resolved here. Sanity Checks can be performed on the generated. To Resolve Blackboxes select Blackboxes and then click next on the bottom left of the window. So select No. Because we want to identify all the potential clocks in the design, selest Yes for the third Question.
And then click Next. It will display the potential clocks in the design as shown below. Check the clocks that need to be included and deleted the ones which are not important. We can omit test clocks which are typically not used in the design.
The following message will be displayed after successful generation of clocks and then click Next in the bottom left window. Select Yes for Verify clock setup. This will run a Sanity Check on the generated clocks.
Click Next to reach the step of creating resets sgdc file. Then click Yes for Edit and complete reset constraints file. Spyglass will identify the potential resets in the Design. Add or Delete resets if tool generates incomplete set of resets. You can set the values for the run in this constraint file.
Click Yes. That is, connectivity, simulation, synthesis and structure. Select Run in Group Mode on top of the window as shown below. Normally Detailed RTL option is selected. The messages will be shown below in the session log as the tool runs the goals. If there are any warning, errors, they will be shown in the session log below. The relevant HDL file will be displayed in the source window. Click Incremental Schematic on the left to open up the schematic window.
Select Goal Setup and Run to select different goals. Now, lets select clock domain crossing. Run the Selected Goal s after selecting the cdc option and then go to Analyze Results.
If you click the incremental schematic on the left of the message tree the relevant incremental schematic looks something like below. We can trace signals from this schematic. To generate reports click on the reports on the top-right of the message tree. Save the project once in a while to save the project information. Likewise, you can select other goals from goals tab to check the design against various rules.
Using Atrenta Spyglass in GUI Mode
Nikokazahn Therefore, to achieve maximum power efficiency, the choice of process technology is paramount. To better manage its long-term strategic growth, TSMC is investing in lighting and solar energy related-industries. Headquartered in Shanghai, China, SMIC has a mm wafer fabrication facility fab and a mm mega-fab in Shanghai; a mm mega-fab and a second majority owned mm fab under development for advance nodes in Beijing; and mm fabs in Tianjin and Shenzhen. Compliance verification services are offered for all VIPs. Naneng Microelectronics is a leading edge semiconductor IP design and IP service provider in China and oversea market. In a short span of time, we have achieved this milestone with manufacturing operations spanning three continents for flexible and secure supply.
ATRENTA SPYGLASS PDF
There are three steps to be performed: 1. Goal Set up and Run: Specify the goals, the severity level of tool run initial rtl, detailed rtl and rtl handoff levels and run the goals. Analyze the results: The results of the tool run on the set up goals are analyzed and reports are generated. Design Setup: a. Adding files: Click Add File s to add design files. They can be automatically generated in latter stages.